μblog: engineering from the trenches

As I had mentioned before, I am slowly working on building a “better” Yagi antenna than my previous rough attempt. I have a lot of work related deadlines and I am also moving next week, so progress will be slow. In any case, I decided to start out with the driven element design and then construct the beam and passive elements afterwards.

I am quite fond of the Fonera wifi router, so I am going to design something that can replace its antenna. For this reason, I am going to put a female SMA connector on the end of my feed cable. I have some RG-174/U cable around the lab which is the right impedance, is fairly thin, but is also lossy. For this reason, I am going to keep the feed cable short enough to mount the Fonera comfortably near the Yagi array. The propagation velocity in the cable is 66% of vacuum, so the wavelength at 2.45GHz is about 8cm. Designing the feed cable to be an integer number of half-wavelengths makes impedance matching a little easier so I made my cable 16 cm from the tip of the connector to the loop hookup.

The signal wavelength in air is a little less than 12.5 cm, so I made my loop out of 3M copper shielding tape and soldered the ends of the tape to the shielding and feed terminals of the cable. I tapered the ends to make the loop line up nicely and took care not to heat the end too much as that will degrade the cable’s dielectric core. One side of the tape has glue on it, which will help mounting the loop on a piece of foam to give it a rigid, rectangular shape.

The helpful folks down the hall let me use their network analyzer to measure the antenna resonance, after a little bit of tuning, I got a peak at about 2.4GHz, which should work fine for lower wifi channel numbers. I also compared this to a commercial wifi antenna from SMC which resonated at about 2.43GHz. Unfortunately, I changed the window width when I tested my loop antenna so that is why the SMC antenna looks like it has more peaks.

My next step is to look up an optimal position of 10-14 director elements in literature and figure out how to fabricate the device. I am thinking of using thick copper wire since this will be an indoor unit. Might use the engraver to drill the holes to specifications.

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Today’s IC Friday entry is the 8bit AVR micro from Atmega. This chip was sent in by a reader, all the way from Iceland.

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In a rare turn of events, I have plagiarized a figure from one of my own writeups. As I have promised before, I wrote up a basic introduction to the necessary electromagnetics and the Yagi-Uda design. This is the first version, so please feel free to comment where I can make some improvements. Thanks goes out to my colleague Eric for helping me proofread this.

( yagi-uda )

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I have been playing around with some wifi networking lately, mostly with the La Fonera, and finally decided to build a directional wifi antenna. Although the cantenna, however, I don’t really like Pringles chips and wanted to make something more interesting. I decided to try and make a simple Yagi antenna with a magnetic dipole as the driving element.

From a construction standpoint, the Yagi antenna is made by spacing conducting rods along the directionality axis with a driving element near one end. It is assumed that the incoming radiation is a TEM plane wave, so the direction of the electric field component should be parallel to the conducting rod orientation. The magnetic component is then perpendicular to the rods and to the directionality of the antenna. The rods spacing is then configured so that the coupled EM field generates a magnetic field component (and a curling electric field component) along the directionality axis of the antenna which has constructive interference at the driving loop. Proper spacing then determines the antenna’s gain and directionality in the band of interest (2.4-2.5GHz).

As a first step, I decided to reproduce the Yagi design made available by Andrew Hakman who reproduced the dimensions of a commercial antenna. This first implementation will test the basic operation and is still missing fine tuning and optimization. I am pretty happy with the initial results which demonstrate a 10dBi gain, which is pretty nice given that it took roughly half an hour to assemble. I will use a more precise construction technique (EGX-300 to mill the main beam) and will work out the optimal metal rod length to magnetic dipole ratio. The main idea is that the loop length needs to support one of the resonant transmission modes for the given frequency while the rods should be as long as possible to increase gain, but shorter than the length of the loop. If anyone wants more info on Yagi theory of operation, please post a comment and I will try to write up a post about it.

To construct this, I used a 0.5×0.5 inch piece of wood for the main beam, and 0.125 inch zinc rods for the conductors. I cut the rods to match the lengths in the above design and sanded the ends to remove any pointy spots. I measured out the positions for the rods on a piece of tape and used a small drill press to make the holes. I then gently tapped the rods into place and removed the tape. I cut the loop out of a sheet of bronze, mainly because that is what I had around. It is better to use a strip (versus a round wire) here to make the loop more sensitive to magnetic field components along the directionality axis. Finally, I decided to minimize transmission losses and mounted a USB 802.11g adapter directly onto the loop. I hot-glued everything into place and went to a large set of windows to test out the contraption.

To benchmark the devices performance, I compared signal strengths to the internal wifi adapter on my Lenovo T60. The signal strengths for the same APs were comparable between the internal adapter and the intact USB adapter so any improvement that I saw here was likely due to the Yagi. Although it was sometimes challenging to find the right direction to point the Yagi, I noted a substantial increase in signal power when I switched Netstumbler between the internal and external wifi adapters.  Over all, I consider this to be a success since I got better performance from the USB adapter by investing a few dollars and a hour of my time. The next version will be forthcoming in the next weeks and will hopefully display even better performance.

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When looking at the application notes section of Fujitsu’s site, I came across their FRAM memory guide book. I was surprised as I did not know what FRAM really was and so I flipped throug. Basically, a film deposition process was developed, which is compatible with standard CMOS processing, that introduces films who can maintain their polarization after the applied electric field is removed. We are all familiar with ferromagnetic devices, these are the pieces of metal that can be magnetized when placed in a constant magnetic field. Thanks to some nice electromagnetic research, we can do something similar with thin films and thereby create ferroelectric capacitors that are capable of retaining data without applied power while being as fast as SDRAM. It is clear that half of the Fujitsu guide is a sales pitch for their ICs, however, the other good is a fairly good introduction to the FRAM technologies. The basic technology is discussed along with some typical ferroelectric substrates. A reference list is also attached.

( mn05-00009-5e.pdf )

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While looking for ways to escape muti-variate calculus purgatory in the final weeks of the semester, I came across Open Math Text.  These are a collection of math books (in PDF and LaTeX) that are openly available for distribution and are aimed at general scholars. A quick look at the collection will show that most of the books are authored by Dr. David Santos, a professor a the Community College of Philadelphia.  It seems that he has written and made available more books, in multiple languages, than the number of scholarly papers that most researchers publish at full universities.

While looking at his personal page, I found another open textbook collection called Textbook Revolution. The obvious downside is that these publications may not go through the same levels of review as textbooks printed at conventional publishers, however, it is nice to know that there is a group of people actively working to make affordable textbooks available.

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As I have mentioned, the semester is winding down and projects are piling up. To help move things along, I have written a pair of documents that outline how to determine the conductivity of a plane (and volume) with a conducting disk (and sphere) of arbitrary size in the middle. I solved Laplace’s equations in both polar and spherical coordinate systems, then used boundary conditions to determine the electric potential and then determined the ratio of applied field to current density to determine the conductivity in the presence of the suspended object. I have checked these early drafts over a few times, however, there may still be some mistakes remaining, so please be warned. Also, feel free to post questions and I will make an attempt to answer them.

( disk-efield.pdf )

( sphere-efield.pdf )

P.S. The photo-op was staged during my last vacation, I would never use Classical Electrodynamics as a coaster.

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The semester is winding down, which means there are a lot of deadlines piling up. One of my deadlines involves re-deriving some work by Hugo Fricke regarding the electrical properties of suspensions of conducting spheres in a conducting medium. Fricke was one of the pioneers of radio-therapy and was one of the first individuals to postulate that blood cells had membranes (instead of being homogeneous solids). He did this through electrical interrogation of blood alone without using any optical techniques. I am posting my step-by-step derivations for the electric potential inside and around a single conducting sphere in a conducting medium with regards to electrostatics. I solve Laplace’s equation using separation of variables in a spherical coordinate system. Hopefully I didn’t make many errors and the rest of the derivation relating total cell conductivity and capacity will follow.

( sphere-efield.pdf ) (Image is from GNU)

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For almost every digital circuit designer out there signal integrity problems often come up as frequencies increase, board sizes decrease and IC pin impedances change. (Every designer except for myself, I work with very low frequency analog circuits!) When signal integrity becomes so poor that unacceptable levels of transmission errors are reached, the efficient digital designer may venture into the analog domain and start looking at transmission line models of their digital traces. For those who prefer to think of everything as analog, this could be the point of argument to “prove” that ones and zeros only exist in the digital designer’s mind and do not represent physical reality (although thinking of voltages as high/low is sometimes more efficient).

Sometime in the 1970s, Motorola introduced digital emitter coupled logic (M ECL) circuits. I don’t know if Motorola was first, however, they had plenty of expertise on the subject. The made ECL useful in those days was the incredibly fast switching rate for these types of logic circuits. ECL works very similarly to standard bi-polar junction transistor based designs, however, the transistors in ECL are always partially conducting. The high and low logic levels are determined by different points along the devices’ load curves which made them faster than BJT devices which had to go from completely off to completely on to switch logic. ECL devices were (and still are) much faster than comparable CMOS devices since CMOS depends on relatively slow thermal generation of carriers to create the conduction region. The point is that fast digital circuits are not that new, and we are facing some of the same transmission line problems as thirty years ago when we scale dimensions and voltages down and increase the operating frequency. If the operating frequencies of interest are such that wave lengths (in the conducting metal trace) are comparable to the length of the trace, transmission line models must be employed. This matter of wavelength can be a tricky question to answer as it can be readily shown that the wavelength of a 60Hz signal in a thick copper conductor is about 5cm (with a phase velocity of only 3.22m/s).

Now that we believe that our traces can act like transmission lines, we are faced with a problem of matching impedance. In the simplest of cases, we have only the driving logic (generator), the trace and the receiving logic (termination). From a driving perspective, the output impedance of the device should closely match the trace impedance, typically something like 30-70Ohms. If the output logic is not matched to the trace, a reflection will not occur at the driving logic in the strict sense, however, the signal traveling down the conducting trace will already be deformed. Now that we have a packet of current traveling down the trace, as specified by the generator, any mismatch in impedance between the trace the termination logic will result in a reflection which will further deform the other current packets traveling down the conductor. This problem can easily happen when CMOS logic (infinite input impedance) is coupled with low output impedance logic and the transmission frequency is gradually increased. The problem becomes more complicated when there are multiple terminations on a given conductor segment as each impedance mismatch generates a reflection and so forth.

Besides the MECL Design Handbook,  Altera provides a few application notes [1][2][3] on signal integrity and high speed design which include termination practices. Typically, introducing a resistor in series or in parallel (to ground) is all that is required to mostly match impedances and give adequate performance, the most important concept is knowing when and where to use these terminating resistors. Although some devices come with various termination options built into the die, most still don’t, so it is good to know when a properly placed resistor network can save a lot of shielding attempts and speed up the debugging process.

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To follow up the last post on resistor selection, here is a the Agilent Technologies Impedance Measurement Handbook. I found this handbook to be quite useful and well written as it covers everything from the basics of measurement problems to examples of both low frequency and RF frequency impedance measurements. The authors focused on the often overlooked parasitic properties of common system components as well as the measurement systems themselves. They go on to outline methods to construct test structures and procedures to minimize these parasitics and go on to give practical examples. For obvious reasons, all of the test equipment in the handbook is made by Agilent, however, other brands can be used just as well.

( 5950-3000.pdf )

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