μblog: engineering from the trenches

Time has not been kind to my isolated stimulator design (above) which has accumulated some additional circuitry over the past few years. The original specifications called for a circuit that would receive a program voltage on the non-isolated side and then drive a load with the same voltage off the isolated side using batteries (not pictured) and return the actual drive voltage and current back to the non-isolated side. The requirement for isolation was pretty relaxed and it was assumed that the load’s common mode potential would be on a few volts from the non-isolated ground.

It was then decided that we needed a voltage-programmed, current-output stimulator, so the same design was slightly modified to have a current follower as the output stage. Due to electrochemical properties of the load, we wanted to clamp the potential between the stimulating electrodes (in current-output mode) to some safety window, so one of the extra circuits was added for this function. As all real electrodes, our electrodes could also polarize, so a small (<1uA) over days could cause some problems with poor performing electrodes. This was a problem due to the single-ended nature of the isolation system. To address this issue, an effective high-pass circuit was carefully added to the isolated side with a time constant of minutes to return the output current to zero, which lead to another small PCB added.

I decided that it was finally time to redesign the stimulator since the kludges were beginning to cause the whole device to fail and were a problem to troubleshoot. The points that I wanted to address specifically are:

• What happens to the isolated output when the non-isolated side loses power (safety!)
• To design a true DC stimulator (no high-pass) while automatically adjusting for offset current
• To introduce full optical isolation
• To provide a warning to the non-isolated side when the isolated side suffers battery failure

The first issue is a big one. Since I am expecting a program voltage which can be positive and negative, the operation of a linear optocoupler requires that the driving LED have some fixed intensity for zero program voltage, with higher and lower intensities for higher and lower program voltage respectively (can be opposite). This means that a power failure on the non-isolated side would shut off the LED completely and would cause the perceived program voltage on the isolated side to rail to one of the supplies, thereby providing maximum stimulation. Looking through several other application notes [1] [2] [3], I did not see a clear solution to this issue. However, using a pair of optocouplers in a differential mode should take care of the problem. That is, still require that both driving LEDs are biased to a certain intensity for zero program voltage, however, only use one to transmit the program voltage and use the other to transmit effective ground. The voltages (or currents) generated by the photovoltaic cells on the isolated side can then be subtracted, and with a little tuning, should provide proper isolation during normal operation and the difference should go to zero when the non-isolated side loses power. Using this differential scheme should also provide a means to control for small offset voltages and should remove the need for a built-in high-pass filter.

The question of full optical isolation is also a tricky one. In the current scheme, the isolated side measures current and voltage and feeds them directly into CMOS inputs of voltage followers on the non-isolated side. This would work fine if the isolated and non-isolated sides are at the same potential, however, any difference creates non-linear current paths through the ESD suppression mechanisms that are built into the CMOS op-amps that we use. I am thinking of using a two or three optocouplers to send the voltage and current signals back to the non-isolated side, however, I will have to work out if I can use the ground from the above paragraph somehow to remove any offsets in their transmission and work to limit the drive current to minimize power usage. The Clare LOC110 (the optocoupler we are using) can easily take 25-50mA across the driving LED, which is more than the rest of the isolated circuitry.

Finally, there needs to be an indicator for battery failure on the isolated side. It can be argued that proper tracking of the stimulation voltage and current would be a good indication of battery condition, but this will not work if the program voltage stays at zero (i.e., if we request zero volts, we will get zero volts out even if the batteries are dead). A compounding problem is that the isolated side is driven by a pair of 1.5V batteries (in series) to provide a total of 3V and it should be remembered that the LEDs in the optocouplers require a minimum of about 1V to operate. Hooking them up to the battery power (one for + and one for -) would be quite a wasteful solution as it would draw a substantial amount of current to operate, especially when the batteries are full. My present design idea is to use a pair of optocouplers, each in series with a depletion-mode FET connected to a resistor bridge. This way, when the bridge voltage drops below a certain value, the depletion-mode FETs will conduct and the LED will turn on, warning of battery failure.

I am hoping to get this design finished before August and fully expect another post in a year with new kludges, perhaps bluetooth or something.

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One of the circuits that I am working on has an optically-isolated sub-circuit which runs on batteries. This is an analog device where the non-isolated input uses LOC110 optocouplers to send some program voltages to the isolated side which then drives a load accordingly and sends back the applied voltage and current back to the non-isolated side. One of the problems with the initial design is maintaining proper signal gain and offset across the optocoupler while the batteries on the isolated side drain.

The LOC110 is a nice device that has an infra-red LED that is driven and a matched pair of photo-resistive elements so that one can be used to control the LED and thereby set the current through the second device. One solution to the problem above was to use a pair of matched voltage references and track the current through the photo-resistive elements while driven at the reference voltage. This proved to be mostly successful, however, it did entail some research regarding voltage reference design.

The most simple voltage reference design involves only one diode operating in a controlled reverse breakdown mode. The exact reverse breakdown voltage depends on the device design (see this post about breakdown mechanisms), however, the general idea is that the current through the device increases very quickly when a certain reverse voltage bias is achieved. One only has to put a resistor in series with the reverse-biased diode that will ensure that the reverse-breakdown criteria are met given the power supply and a voltage reference is born. The devoted fan of μblog will surely exclaim: But Nick! Didn’t you use a reverse-biased diode as a temperature sensor once? What good is a voltage reference that varies with temperature? I would agree completely and exclaim that datasheets for voltage references display the equivalent circuit model of a diode in reverse breakdown, however, the actual designs are a bit more complicated.

This application note from Analog Devices provides some good insights into designing single-technology voltage references. The basic idea in many cases is to create a differential voltage by building mismatched devices or by introducing resistances, such as R3 above, and then using an amplifier to generate a reference voltage. To maintain good stability over a temperature range, the amplifier can be designed to increase gain in order to compensate for the beta degradation at higher temperatures. It is still possible to do all of this using a bi-polar process by designing biasing current sources that change appropriately with temperature. It is also possible, although more difficult, to introduce FET devices which can have opposite thermal effects as compared to BJTs. In this case, it would be fairly straight forward to increase the gain of the difference amplifier through increased FET trans-conductances with increased temperatures.

In the end, I still have some drift and offset problems that are not associated with temperature, however, the design process has been a good introduction to and has developed an appreciation for voltage reference designs.

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For almost every digital circuit designer out there signal integrity problems often come up as frequencies increase, board sizes decrease and IC pin impedances change. (Every designer except for myself, I work with very low frequency analog circuits!) When signal integrity becomes so poor that unacceptable levels of transmission errors are reached, the efficient digital designer may venture into the analog domain and start looking at transmission line models of their digital traces. For those who prefer to think of everything as analog, this could be the point of argument to “prove” that ones and zeros only exist in the digital designer’s mind and do not represent physical reality (although thinking of voltages as high/low is sometimes more efficient).

Sometime in the 1970s, Motorola introduced digital emitter coupled logic (M ECL) circuits. I don’t know if Motorola was first, however, they had plenty of expertise on the subject. The made ECL useful in those days was the incredibly fast switching rate for these types of logic circuits. ECL works very similarly to standard bi-polar junction transistor based designs, however, the transistors in ECL are always partially conducting. The high and low logic levels are determined by different points along the devices’ load curves which made them faster than BJT devices which had to go from completely off to completely on to switch logic. ECL devices were (and still are) much faster than comparable CMOS devices since CMOS depends on relatively slow thermal generation of carriers to create the conduction region. The point is that fast digital circuits are not that new, and we are facing some of the same transmission line problems as thirty years ago when we scale dimensions and voltages down and increase the operating frequency. If the operating frequencies of interest are such that wave lengths (in the conducting metal trace) are comparable to the length of the trace, transmission line models must be employed. This matter of wavelength can be a tricky question to answer as it can be readily shown that the wavelength of a 60Hz signal in a thick copper conductor is about 5cm (with a phase velocity of only 3.22m/s).

Now that we believe that our traces can act like transmission lines, we are faced with a problem of matching impedance. In the simplest of cases, we have only the driving logic (generator), the trace and the receiving logic (termination). From a driving perspective, the output impedance of the device should closely match the trace impedance, typically something like 30-70Ohms. If the output logic is not matched to the trace, a reflection will not occur at the driving logic in the strict sense, however, the signal traveling down the conducting trace will already be deformed. Now that we have a packet of current traveling down the trace, as specified by the generator, any mismatch in impedance between the trace the termination logic will result in a reflection which will further deform the other current packets traveling down the conductor. This problem can easily happen when CMOS logic (infinite input impedance) is coupled with low output impedance logic and the transmission frequency is gradually increased. The problem becomes more complicated when there are multiple terminations on a given conductor segment as each impedance mismatch generates a reflection and so forth.

Besides the MECL Design Handbook,  Altera provides a few application notes [1][2][3] on signal integrity and high speed design which include termination practices. Typically, introducing a resistor in series or in parallel (to ground) is all that is required to mostly match impedances and give adequate performance, the most important concept is knowing when and where to use these terminating resistors. Although some devices come with various termination options built into the die, most still don’t, so it is good to know when a properly placed resistor network can save a lot of shielding attempts and speed up the debugging process.

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In my battle with transfer function estimation, I have been dealing with many noise problems lately and have come across this application note from TI regarding the calculation of noise figures for basic op-amp circuits.  This noise figure deals with the ratio of circuit signal-to-noise ratio (SNR) at the input versus the output. The article goes through the derivation of noise analysis equations due to thermal noise in resistive elements and due to rms noise figures of the active device and goes on to quantify the noise figure as a function of temperature, resistances and op-amp parameters. This can be useful in determining performance properties of circuits given a set of passive components and can be used to define a “best case scenario”.

This all well and good, but then one might ask what noise has to do with system identification (transfer function estimation)? The simple answer is that the frequency-domain transfer function can be determined by passing “noise” through a system and comparing the spectral properties of the output versus the input. The idea is that white noise has a flat spectra (over infinite time) so the transfer function can be accurately determined for all frequencies (again, given infinite time). If infinity is too long a time to wait, one trick is using something called periodic random noise to give a well defined spectral distribution in finite time. A Gaussian random number generator can create white noise, however, an inverse Fourier transform is used to to generate the periodic noise.

Essentially, enough sinusoids are added together to cover the frequency range of interest with equal amplitudes and randomized phases that are distributed over +/- pi. The amplitude will relate to the desired resulting rms value for the noise and the number of summed sinusoids. The frequencies of choice should line up with the sampled frequencies in the following FFT that will be computed to compare the spectra of the input and output signals. The signal will now look like noise and will be “random”, however, all of the frequency domain components will maintain their amplitude and phase through the whole procedure leading to less variance in the FFTs.

( slyt094.pdf )

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It is true that I hold a high regard for current sources due to their limitless applications in the biosciences. Current sources are at the heart of electroplating systems for electrode manufacture, stimulation of tissue and imaging. This is only a small part of the reason that I find this 1973 application note so appealing. The most important message, to me, is the complete walk-through from the basic governing equations based on ideal op-amps, to non-ideal characteristics, to error propagation.

In this case, the current source becomes less important than the design process. One of the subtle issues that can be seen from the equations is that resistor matching can degrade circuit accuracy just as much as the op-amp quality. For this reason, it may be beneficial to spend an $0.05 on more accurate resistors and save $1.00 on an op-amp. The converse is also true: you can spend an extra $1.00 on a more precise op-amp to save $0.05 on passive components. The standard error from your complete circuit may end up being comparable in the two cases.

( an587-d.pdf )

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Although Wolfson Microelectronics produces some fine integrated circuits, their application note section is somewhat out of the way and doesn’t like to be linked to directly. This didn’t stop me from looking around and finding some potentially useful app notes:

A.C. Coupling Capacitor Selection

Recommended Output Filters for Wolfson Audio DACs 

Class D Headphone Filter Component Selection

Issues When Grounding D.C. Coupled Headphone Outputs

The main reason that I was looking there in the first place was that I was getting excessive noise when coupling a portable audio player to an audio system I am working on and couldn’t figure out why. When I took everything apart, I found that output stage of the audio device was being pulled up to a higher voltage than expected by the coupling on the input stage and thereby biasing the input stage of the audio amplifier incorrectly. After some careful circuit modifications, the signal integrity was returned with fairly good low frequency response. At this point, my audio circuit experience is still minimal, I hope to post some designs once I get something worthwhile going.

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I can’t help but confess that the past few days, after getting Orange Box for Christmas, have been excellent for me, but a total waste of time for everyone else. I spent the past two days playing Half Life 2 and Portal and not much else.

The apology aside, I have become quite curious about the Nike+iPod gift that June received. The box contains exactly what it shows: one foot sensor and one receiver for the iPod Nano. I have seen a few teardowns (1) (2) and am pretty impressed. Just for the record, neither of the devices are serviceable, so the shoe sensor must be replaced every after every “1000 hours of use“. The basic idea is that the shoe sensor has a piezoelectric sensor to measure acceleration (even though many people think there is a MEMS sensor)  that sends it’s identification code to the iPod receiver. The two are coupled and supported by the latest iPod Nano firmware, which then provides voice notifications and on-line tracking.

Over all, this is a nice technology that demonstrates power conservation practices (runs from a 3.6V li-ion cell). The design is sleek and efficient. I hope to post the details to make an adapter for this device to another shoe brand soon. I hope this did not sound too much like a sales advertisement for you, the smartest reader on the internet, to see.

Finally, there is a paper from U of Washington which basically outlines how to track someone based on their Nike+iPod gear. They outline the serial communication protocol between the attachment and the iPod.

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As per my previous post, I have started working out the waveforms to interface a Sony dualshock 2 controller. I decided to go with a Cypress PSoC instead of a standard 8051 because it has a built in SPI controller thereby making the bit-banging much easier. The downside is that I don’t have a C compiler built into the development suite, but that is all right, I am pretty good with assembly. In the process of setting this board up and testing a few things, I found the embedded systems section of wikibooks quite useful. The whole electrical engineering section looks pretty good. The pages can be edited by anonymous readers just as easily as wikipedia, however, I have not found anything terribly wrong in the limited time I spent looking at the site. Over all, it seems like a decent place to learn for beginners and to contribute for experts.

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Here is a short application note (AN-404) from Analog Devices that deals with high performance analog and digital layout on the same printed circuit board.  The specific example deals with AD1845 and CS4231 codecs and demonstrates some ideas for clean power and ground plane separation, among others. The application note provides some handy numbers, such as a “ballpark” estimate inductance of a PCB trace of 1nH/mm. Another helpful hint is that the note helps prioritize the various pins of the codec on page six to optimize noise management.

While on the subject of PCB design, here is a nice tutorial covering various dielectric materials used in printed circuit board fabrication. Its main goal is to give an overview of the various properties of the materials so the designer has a better judgement of which to use for higher performance RF boards and which is most economic for medium-speed digital designs.

( an-404.pdf )

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What to do when you need to mount a ball-grid array (BGA) package on a circuit board without sophisticated equipment? One popular option is to create something called a “reflow oven” which is able to control your circuit boards temperature with respect to time. The idea behind reflow soldering is that we may want to apply a thin layer of solder paste (solder with flux) over the exposed pads on a printed circuit board, then place all of the surface-mount components on that side, and then heat the board so the solder melts and the components become electrically attached. This is pretty much the only method for attaching components whose pads are completely on the underside making them inaccessible to soldering irons. The temperature profile is fairly standardized (here, here and here) and consists of first removing any excess moisture from the packages, then ramping up to the temperature required to melt the solder, then to cool off in a safe manner that prevents component or joint damage. It should be noted that these temperature profiles aim to limit the time components spend at elevated temperatures (>250C) to minimize the risk of damage due to heat.

What I am proposing is something much simpler: lets use a hot  plate to heat the PCB and achieve the same sort of reflow process. The main disadvantage is that the process is much less controlled and the dimensions of the board must be small enough to fit on the hotplate. The primary benefits are its simplicity. I am fortunate enough to have a hotplate which has a thermocouple to the surface and can measure the surface temperature with some degree of proficiency, so an alternate method will be required for other types. Some kind of infra-red measurement method would probably work well.

The idea is that we first apply solder paste to the board, when necessary. In this example, I am mounting a MICROSMD8 package where there is ample solder on the board and the chip to achieve connection. It is often a good idea to put some clean-free flux on the board in any case. Everything is first pre-heated for ten minutes at 50-80C to get rid of some of the moisture. The assembly is then heated to about 230C. At this point, the chips should already be aligned over the target pads. The reason for this temperature is that unlike the oven, the top surface of the PCB is exposed to air and thereby creates a thermal gradient. We need to control the heat on the top surface so that the solder just barely melts. This can be noted when watching the PCB under a microscope or with a magnifying glass as the solder will become very shiny when it melts.  As the solder melts on the chips and PCB, the surface tension will pull the chip into alignment. The whole assembly can then be slowly cooled and tested electrically. When populating larger projects, it is best to put on the larger chips first and then place something to act as a heat-sink on top. I have had success with larger DSP chips where I placed inverted bolts on top to radiate away some of their heat while adjusting other components. Finally, don’t forget that a cold PCB looks the same as a hot one, so be sure to avoid burning yourself.

( an081.pdf ) ( an353.pdf ) ( xapp427.pdf )

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