For almost every digital circuit designer out there signal integrity problems often come up as frequencies increase, board sizes decrease and IC pin impedances change. (Every designer except for myself, I work with very low frequency analog circuits!) When signal integrity becomes so poor that unacceptable levels of transmission errors are reached, the efficient digital designer may venture into the analog domain and start looking at transmission line models of their digital traces. For those who prefer to think of everything as analog, this could be the point of argument to “prove” that ones and zeros only exist in the digital designer’s mind and do not represent physical reality (although thinking of voltages as high/low is sometimes more efficient).
Sometime in the 1970s, Motorola introduced digital emitter coupled logic (M ECL) circuits. I don’t know if Motorola was first, however, they had plenty of expertise on the subject. The made ECL useful in those days was the incredibly fast switching rate for these types of logic circuits. ECL works very similarly to standard bi-polar junction transistor based designs, however, the transistors in ECL are always partially conducting. The high and low logic levels are determined by different points along the devices’ load curves which made them faster than BJT devices which had to go from completely off to completely on to switch logic. ECL devices were (and still are) much faster than comparable CMOS devices since CMOS depends on relatively slow thermal generation of carriers to create the conduction region. The point is that fast digital circuits are not that new, and we are facing some of the same transmission line problems as thirty years ago when we scale dimensions and voltages down and increase the operating frequency. If the operating frequencies of interest are such that wave lengths (in the conducting metal trace) are comparable to the length of the trace, transmission line models must be employed. This matter of wavelength can be a tricky question to answer as it can be readily shown that the wavelength of a 60Hz signal in a thick copper conductor is about 5cm (with a phase velocity of only 3.22m/s).
Now that we believe that our traces can act like transmission lines, we are faced with a problem of matching impedance. In the simplest of cases, we have only the driving logic (generator), the trace and the receiving logic (termination). From a driving perspective, the output impedance of the device should closely match the trace impedance, typically something like 30-70Ohms. If the output logic is not matched to the trace, a reflection will not occur at the driving logic in the strict sense, however, the signal traveling down the conducting trace will already be deformed. Now that we have a packet of current traveling down the trace, as specified by the generator, any mismatch in impedance between the trace the termination logic will result in a reflection which will further deform the other current packets traveling down the conductor. This problem can easily happen when CMOS logic (infinite input impedance) is coupled with low output impedance logic and the transmission frequency is gradually increased. The problem becomes more complicated when there are multiple terminations on a given conductor segment as each impedance mismatch generates a reflection and so forth.
Besides the MECL Design Handbook, Altera provides a few application notes  on signal integrity and high speed design which include termination practices. Typically, introducing a resistor in series or in parallel (to ground) is all that is required to mostly match impedances and give adequate performance, the most important concept is knowing when and where to use these terminating resistors. Although some devices come with various termination options built into the die, most still don’t, so it is good to know when a properly placed resistor network can save a lot of shielding attempts and speed up the debugging process.