μblog: engineering from the trenches

The semester is winding down, which means there are a lot of deadlines piling up. One of my deadlines involves re-deriving some work by Hugo Fricke regarding the electrical properties of suspensions of conducting spheres in a conducting medium. Fricke was one of the pioneers of radio-therapy and was one of the first individuals to postulate that blood cells had membranes (instead of being homogeneous solids). He did this through electrical interrogation of blood alone without using any optical techniques. I am posting my step-by-step derivations for the electric potential inside and around a single conducting sphere in a conducting medium with regards to electrostatics. I solve Laplace’s equation using separation of variables in a spherical coordinate system. Hopefully I didn’t make many errors and the rest of the derivation relating total cell conductivity and capacity will follow.

( sphere-efield.pdf ) (Image is from GNU)

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Since I have started the IC Friday weekly section, I have accumulated a significant number of exposed dies. In a general effort to reduce clutter, I would like to give these away as it is unlikely that I will refer to the dies in the future. The 70 or so dies will be split into two categories, digital and analog, and each will be mailed to a random commenter using the US Postal Service. If you are interested, leave a comment below indicating your preference for digital or analog dies. Please use a valid email address when making the reply, I will need it to contact you and it will not be displayed to the public. I will keep this open for two weeks and will let MATLAB (2008a) decide the winners on May 9th. Good luck and feel free to post any questions.

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For almost every digital circuit designer out there signal integrity problems often come up as frequencies increase, board sizes decrease and IC pin impedances change. (Every designer except for myself, I work with very low frequency analog circuits!) When signal integrity becomes so poor that unacceptable levels of transmission errors are reached, the efficient digital designer may venture into the analog domain and start looking at transmission line models of their digital traces. For those who prefer to think of everything as analog, this could be the point of argument to “prove” that ones and zeros only exist in the digital designer’s mind and do not represent physical reality (although thinking of voltages as high/low is sometimes more efficient).

Sometime in the 1970s, Motorola introduced digital emitter coupled logic (M ECL) circuits. I don’t know if Motorola was first, however, they had plenty of expertise on the subject. The made ECL useful in those days was the incredibly fast switching rate for these types of logic circuits. ECL works very similarly to standard bi-polar junction transistor based designs, however, the transistors in ECL are always partially conducting. The high and low logic levels are determined by different points along the devices’ load curves which made them faster than BJT devices which had to go from completely off to completely on to switch logic. ECL devices were (and still are) much faster than comparable CMOS devices since CMOS depends on relatively slow thermal generation of carriers to create the conduction region. The point is that fast digital circuits are not that new, and we are facing some of the same transmission line problems as thirty years ago when we scale dimensions and voltages down and increase the operating frequency. If the operating frequencies of interest are such that wave lengths (in the conducting metal trace) are comparable to the length of the trace, transmission line models must be employed. This matter of wavelength can be a tricky question to answer as it can be readily shown that the wavelength of a 60Hz signal in a thick copper conductor is about 5cm (with a phase velocity of only 3.22m/s).

Now that we believe that our traces can act like transmission lines, we are faced with a problem of matching impedance. In the simplest of cases, we have only the driving logic (generator), the trace and the receiving logic (termination). From a driving perspective, the output impedance of the device should closely match the trace impedance, typically something like 30-70Ohms. If the output logic is not matched to the trace, a reflection will not occur at the driving logic in the strict sense, however, the signal traveling down the conducting trace will already be deformed. Now that we have a packet of current traveling down the trace, as specified by the generator, any mismatch in impedance between the trace the termination logic will result in a reflection which will further deform the other current packets traveling down the conductor. This problem can easily happen when CMOS logic (infinite input impedance) is coupled with low output impedance logic and the transmission frequency is gradually increased. The problem becomes more complicated when there are multiple terminations on a given conductor segment as each impedance mismatch generates a reflection and so forth.

Besides the MECL Design Handbook,  Altera provides a few application notes [1][2][3] on signal integrity and high speed design which include termination practices. Typically, introducing a resistor in series or in parallel (to ground) is all that is required to mostly match impedances and give adequate performance, the most important concept is knowing when and where to use these terminating resistors. Although some devices come with various termination options built into the die, most still don’t, so it is good to know when a properly placed resistor network can save a lot of shielding attempts and speed up the debugging process.

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Over a decade ago, I remember printing out and reading a text by Aleph1 entitled Smashing the Stack for Fun and Profit. Back then, stack-based buffer overflows were a hot topic and the tide was turning as programmers began to realize that null termination of strings was not a good security measure and bounds checking was becoming necessary for the security-minded programs.

The issue was that many people were used to using a function like strcpy() to copy a string from one memory location to a dynamically allocated memory segment on the stack. The strcpy() function simply started copying from the supplied address and stopped when it reached a null character without knowing how much space was allocated for the string at the destination. As a result, segments of the stack that were not allocated for the “local” variable, like the return address of a function, could be overwritten with arbitrary values. With the properly formatted string, even executable code could be put somewhere on the stack and the return address could be overwritten so that this code could be executed, for fun and profit as they say. Programmers became wiser and started using strncpy() instead, which only copied a fixed amount of data and therefore guaranteed that the allocated space would not be exceeded. Furthermore, most modern operating systems can now set areas of the memory dedicated to the stack as non-executable, so the above routine would be foiled. Individuals have found some ways around these security features, however, the stack smashing exploit (as described by Aleph1) has mostly been considered a thing of the past.

I use the term mostly since Nintendo has preserved the knowledge and allowed practice of this exploit with their release of the latest Zelda game for the Wii. Through a cleverly crafted save file, the name of the main characters horse can contain a string as mentioned above and lead to execution of arbitrary code. There are a few tricks to maintain the integrity of the save file, however, after a decade the above exploit still lives on, almost in the same form as described by Aleph1.

( Although the picture is not from the Twilight Princess game, it is a good game none the less. )

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Today, we are presented with the venerable i386 processor which kicked off the 32bit era for the x86 architecture. This one happens to have a math-coprocessor on board as well.

i386-4x-stitch.jpg

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To follow up the last post on resistor selection, here is a the Agilent Technologies Impedance Measurement Handbook. I found this handbook to be quite useful and well written as it covers everything from the basics of measurement problems to examples of both low frequency and RF frequency impedance measurements. The authors focused on the often overlooked parasitic properties of common system components as well as the measurement systems themselves. They go on to outline methods to construct test structures and procedures to minimize these parasitics and go on to give practical examples. For obvious reasons, all of the test equipment in the handbook is made by Agilent, however, other brands can be used just as well.

( 5950-3000.pdf )

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In all of my undergraduate and graduate career, I have had very little introduction to passive component selection. Most of what I know come at the expense of poor designs and from Bob Pease’s book on troubleshooting analog circuits. It should be known that resistors typically have small associated capacitances and inductances which can lead to strange circuit effects, however, this application note focuses mostly on selecting the right resistor based on power rating.

As circuits get smaller, using a something as small as a 0201 format resistor becomes fairly attractive. The downside (there are always downsides!) is that as the package size goes down, so does the power rating. Other factors, like enclosure and cooling, can change the rated dissipation limit. Although the app note covers many of these factors, they also provide a useful “shortcut” sheet on the seventh page to simplify the possible de-rating calculations for a particular circuit design. This information is still missing from many third year EE circuit design courses, so hopefully this PDF will provide an adequate supplement.

( appnotes_res_select.pdf )

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As promised last week, here is the MAX 660. With computer issues resolved, we now have pictures. Thanks go out to Neil B. for supplying me with this chip.

max660-10x-stitch.jpg

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I decided to sign up to do Tour de Cure this year (in June) to help raise funds and awareness for diabetes research. The event I will be in is the 100km ride in Reston, VA along the W&OD trail. If anyone would like to offer sponsorship (in any value), I would gladly accept. The link to make a donation is at the bottom of the page and the donation is tax-deductible (in the USA at least). Please post any comments or questions you may have and wish me luck. Conversely, if you will be in the Washington D.C. area and are interested in doing this, you can join my friends any I and make it a team effort.

( Donation page for N. Chernyy )

P.S. For extra kicks, the bike above is the one that I will be doing the 100km on. It is not a road bike, but it is really well tuned and rides smoothly.

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The fine people over at FaradNet have put together an appreciable set of notes on the electrolytic capacitors that appear in almost all consumer electronics devices. Although this is a good read for those who are interested using the devices in a safe manner (and getting the most performance out of them), there is a lot of text, so I will try to summarize the two features of electrolytics that seem to be most important: polarization and frequency response.

To understand the principle behind the polarization of the device, we must think of a little bit of electrochemistry. The electrolytic capacitor can be thought of as two electrodes with an electrolyte (substance containing free ions that can pass charge) between. If we neglect the circuit outside of the capacitor, we have only the two electrode-electrolyte interfaces to consider. From a manufacturing stand point, we can make one of the interfaces matter more than the other, so we can essentially form a rectifying system. Just as the diode stores energy in the depletion region when it is reverse biased (below breakdown), the “important” electrode-electrolyte interface can store energy when the applied voltage is biased in such a way as it is unfavorable for charge to flow across. This ability to store energy due to electric is the source of the capacitance in a dielectric capacitor. Just as the diode, forward bias conditions can lead to a large current even at small applied voltages, this current damages the electrode-electrolyte interfaces and generates heat which can further damage the device. For this reason, the capacitor polarization should be closely followed to prevent damage to the device or to the device operator if the capacitor is really abused.

At this point, it would seem that using the device in an AC circuit would require additional design considerations to maintain proper polarization at all times. This is true, however, there are other issues with electrolytic capacitors that pertain to AC circuits. The ability to store charge at the electrode-electrolyte layer has some dependence on ion mobility in the electrolyte which can be substantially slower than deformation of electron orbits in a tantalum dielectric. This causes the capacitance to drop off, sometimes substantially, as the signal frequency increases. For example, this would cause a low-pass filter to roll off at a slower-than-expected rate. The exact frequency-dependent change in capacitance is not the same for all electrolytics and will depend both capacitor design and its state. This why electrolytic capacitors are often left to DC applications such as decoupling and power regulation.

Hope this was informative and remember, safety first, performance second.

[ Image is from Tim Reese's page. ]

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