Tue 25 Sep 2007
Since Orcad Layout has reached its end of life, I have started working with Allegro PCB Editor. While making some footprints, I stumbled across this repository of package and recommended land dimensions at Fairchild Semiconductor. I hope this is not a mistake by the webmaster and they keep the directory viewable. In either case, it is a good set of information to archive.
( sc705_dim.pdf )
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September 26th, 2007 at 12:21 am
Do you know if allegro does schematics as well? or just PCBs? Right now I use Eagle, but I’m always on the lookout for something better.
September 26th, 2007 at 6:32 am
Hi Paul,
The Cadence suite has what is called Allegro Design Entry HDL and Allegro Design Entry CIS which are an integrated digital and analog/mixed signal design flow respectively. I use CIS mostly which has a fairly nice schematic entry and PSPICE based simulation. Hope this helps.
September 26th, 2007 at 4:58 pm
Thank-you very much. I was just talking to the Allegro fellows about getting a demo copy, I guess don’t they have it available for the Allegro stuff but only for OrCAD 15.7. I’m downloading it right now. How do you find it for creating your own library parts?
Also, I would like to mention how much I enjoy your IC fridays. It’s fascinating to actually see the die on these chips.
September 26th, 2007 at 7:56 pm
Thanks for the kind comments! Creating library parts for the schematic entry is pretty straightforward, just draw a shape and place the pins. Alternatively, you can have it automatically create a schematic symbol based on a SPICE model. Creating PCB footprints is also easy, first you make the padstack for the pins and then you arrange them and add all the artwork. I am documenting my learning experience with Allegro PCB Editor (what should be included with Cadence SBP 15.7). I can post the howto pertaining to making PCB footprints if you think that will be helpful. If you have some ICs that you want to see imaged, feel free to send them in!
October 10th, 2007 at 5:03 pm
[...] a small follow-up to my post about package footprints, here is a Packaging Databook from Intel. About half of the book is on the physical [...]