μblog: engineering from the trenches

Here is a short (~30 minutes, 41MB) drum and bass mix done by myself as a result of cleaning out my record collection:

nchernyy-070924.mp3

The tracklist is available here:

nchernyy-070924-tracklist.txt

Most of these records are at least 3-5 years old so keep that in mind. If there is a positive response, I may end up posting a few more of these so please enjoy!

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Today’s subject is the REF1004-1.2 voltage reference from Texas Instruments.  The datasheet diagram makes it seem that the chip is simply a single diode, however, it is clear that additional components are required to realize temperature stability. The contact on the top left is what TI refers to as the “cathode” while the contact on the bottom right is the “anode”.

ref1004-1_2-10x-stitched.jpg

( ref1004-12.pdf )

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Since Orcad Layout has reached its end of life, I have started working with Allegro PCB Editor. While making some footprints, I stumbled across this repository of package and recommended land dimensions at Fairchild Semiconductor. I hope this is not a mistake by the webmaster and they keep the directory viewable. In either case, it is a good set of information to archive.

( sc705_dim.pdf )

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I have been noticing more and more the tendency of tutorials or help information on the fast Fourier transform (FFT) to completely ignore signal windowing/enveloping/tapering. The sample code typically starts out with generating a time series made up of one or more sinusoids with possible random noise included. The code then takes an FFT of the data and displays the power spectra. This simple method works well for a small class of signals whose properties are not changing over the time bin and whose values go to zero at the start and end of the time bin. In all other cases, there is some degree of spectral leakage, or unnecessary broadening of spectral peaks and potential additional spectral noise. The typical solution to this problem to subdivide the whole time series into overlapping time-bins and then apply some kind of window function and only then perform a FFT. Care should be taken to normalize the resulting FFT with the area of the window function so that accurate power values are preserved. Things get more complicated if the time series under analysis deals with point processes, something which may be described later. The image above is a μblog original and may be used freely.

( an014-understanding-fft-windows.pdf )

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This week’s IC Friday focuses on the LTC4066 from Linear Technology. This is USB power management chip with Li-ion battery charging capabilities. While the datasheet is not publicly available, it is potentially possible to obtain it by emailing Linear’s sales people.

ltc4066-10x-stitched.jpg

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If anyone has had their computer crash due to very brief power flicker, you can sleep better knowing that there Information Technology Industry Council is working hard to keep you on-line. I started reading a book on power delivery and quality and have found this figure above, the CBEMA/ITIC curve. The idea is that power supplies and systems in “information technology” are designed to comply with certain voltage tolerances, or rather tolerate certain deviations from the normal 120Vac@60Hz (in the U.S.A.) for specified amounts of time. For example, this type of equipment is supposed to tolerate a total loss of power for one half of a cycle without interruption. Conversely, the same equipment is supposed to tolerate a voltage surge of 500% of the nominal value for 1% of a total cycle period.

After looking deeper, I also located a SEMI F47 power standard which applies to manufacturers of equipment and subsystems destined for semiconductor manufacturing. This standard is not as rigorous as the one above and is only specified for voltage sags. It can be seen that this type of equipment must be tolerant of a reduction of line voltage to 50% of nominal value for up to 0.2 seconds on a single phase system or on one phase to neutral for a three-phase system. A presentation covering updates to the SEMI F47 standard is available here.

(  voltage_tolerance.pdf )

( semi_standards.pdf )

( 4overviewofsemif47-0706.pdf )

( iticurv.pdf )

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Last week, I wrote an entry where I  pointed out some methods to aid with getting your SPICE simulation to converge and made a promise that I would write a guide that would go through all the necessary steps to create a simulation with a non-standard device. Luckily, the fine folks at Texas Instruments have already written such a guide. The guide is designed to work with the Orcad/Cadence suite and guides the user through all the steps, starting with downloading a SPICE model from ti.com to changing the appearance of the schematic symbol to creating a simulation profile and running the simulation. Although this is geared towards Texas Instruments, the ideas are generic enough to apply to practically any vendor’s models.

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This week’s feature is the audio/video CODEC from Wolfson (often misspelled as Wolfsom). I don’t yet have the datasheet for this device but it is from the iPhone and can reportedly be found in some of the video iPods. It is difficult to distinguish the parts of the chip in their function, however, it is interesting to note that the device seems to have both EEPROM and RAM providing the possibility for some level of “firmware”. It can be seen that Wolfson is a Scottish company both on their website and on the die with a small image of Scotland.

Update: It appears that I made a mistake and the chip number should actually read WM8758BG (see iFixit), not WM87588G. Sorry about the confusion.

wm87588g-10x-stitched.jpg

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I recently found another free tool (in addition to LASI) that allows users to play around with CMOS layout (and some very basic simulation). The tool is from Microwind Inc with the lite version aptly named “Microwind“. Once the user form is filled out with minimal information, various tools can be downloaded with an assortment of papers including a 4-bit microprocessor example. The lite version of the tool is somewhat limited, but there are some simple layout examples. Furthermore, this is the tool used to demonstrate all of the examples in Basic CMOS Cell Design (Amazon) and Advanced CMOS Cell Design (Amazon) by Sicard (author of the software) and Bendhia. I have read most of the first book and am working on the second one and will write a short review when both are completed. So far, the first (Basic) one is all-right for a reference but requires some thinking to understand a few of the layouts. The image above is a example layout for a 3-bit DAC.

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Although SPICE is one of the most prevelant tools for analog circuit simulation, saying that it was without problems would be incorrect. The problem that I have seen is that individuals start using a cad package, such as the Cadence/Orcad suite and run into some incomprehensible problems with analog simulation with PSPICE and quickly give up on the technology deeming it unusable. What needs to be understood is that the simulation heavily relies on numerical integration and matrix inversion methods, both of which are very susceptible to numerical errors. The up-side is that there are parameters that can be tuned, and in some cases, simulation speed/performance can be sacrificed to get higher accuracy and convergence.

Charles Hymowitz, from Intusoft, has written a small article on the topic of SPICE simulation convergence. The basic idea here is to first make sure your circuit is wired as intended and that the nodes are properly labeled. He then gives an overview of some parameters and algorithms that can be tweaked to try to attain convergence. Finally, he makes a very important point: if your circuit still doesn’t converge, look back at the design, there may be something inherently wrong with it.

I agree with most of his statements and have been using SPICE for some time to get a high-level simulation of various analog circuits. Unfortunately, it is not a substitution for building a prototype, but it does offer assistance with initial design. I am thinking of writing up a few step by step guides for using the Orcad suite, including one that demonstrates PSPICE simulation with device models downloaded from vendor web sites. If anyone is interested in seeing those types of things, send an email or leave a comment and I may do it a bit quicker.

( converg.pdf )

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