Today’s subject is the REF1004-1.2 voltage reference from Texas Instruments. The datasheet diagram makes it seem that the chip is simply a single diode, however, it is clear that additional components are required to realize temperature stability. The contact on the top left is what TI refers to as the “cathode” while the contact on the bottom right is the “anode”.
( ref1004-12.pdf )
Since Orcad Layout has reached its end of life, pills I have started working with Allegro PCB Editor. While making some footprints, advice I stumbled across this repository of package and recommended land dimensions at Fairchild Semiconductor. I hope this is not a mistake by the webmaster and they keep the directory viewable. In either case, it is a good set of information to archive.
( sc705_dim.pdf )
I have been noticing more and more the tendency of tutorials or help information on the fast Fourier transform (FFT) to completely ignore signal windowing/enveloping/tapering. The sample code typically starts out with generating a time series made up of one or more sinusoids with possible random noise included. The code then takes an FFT of the data and displays the power spectra. This simple method works well for a small class of signals whose properties are not changing over the time bin and whose values go to zero at the start and end of the time bin. In all other cases, check there is some degree of spectral leakage, there or unnecessary broadening of spectral peaks and potential additional spectral noise. The typical solution to this problem to subdivide the whole time series into overlapping time-bins and then apply some kind of window function and only then perform a FFT. Care should be taken to normalize the resulting FFT with the area of the window function so that accurate power values are preserved. Things get more complicated if the time series under analysis deals with point processes, mind something which may be described later. The image above is a μblog original and may be used freely.
( an014-understanding-fft-windows.pdf )
If anyone has had their computer crash due to very brief power flicker, order you can sleep better knowing that there Information Technology Industry Council is working hard to keep you on-line. I started reading a book on power delivery and quality and have found this figure above, the CBEMA/ITIC curve. The idea is that power supplies and systems in “information technology” are designed to comply with certain voltage tolerances, or rather tolerate certain deviations from the normal 120Vac@60Hz (in the U.S.A.) for specified amounts of time. For example, this type of equipment is supposed to tolerate a total loss of power for one half of a cycle without interruption. Conversely, the same equipment is supposed to tolerate a voltage surge of 500% of the nominal value for 1% of a total cycle period.
After looking deeper, I also located a SEMI F47 power standard which applies to manufacturers of equipment and subsystems destined for semiconductor manufacturing. This standard is not as rigorous as the one above and is only specified for voltage sags. It can be seen that this type of equipment must be tolerant of a reduction of line voltage to 50% of nominal value for up to 0.2 seconds on a single phase system or on one phase to neutral for a three-phase system. A presentation covering updates to the SEMI F47 standard is available here.
( voltage_tolerance.pdf )
( semi_standards.pdf )
( 4overviewofsemif47-0706.pdf )
( iticurv.pdf )
Last week, I wrote an entry where I pointed out some methods to aid with getting your SPICE simulation to converge and made a promise that I would write a guide that would go through all the necessary steps to create a simulation with a non-standard device. Luckily, the fine folks at Texas Instruments have already written such a guide. The guide is designed to work with the Orcad/Cadence suite and guides the user through all the steps, starting with downloading a SPICE model from ti.com to changing the appearance of the schematic symbol to creating a simulation profile and running the simulation. Although this is geared towards Texas Instruments, the ideas are generic enough to apply to practically any vendor’s models.
I recently found another free tool (in addition to LASI) that allows users to play around with CMOS layout (and some very basic simulation). The tool is from Microwind Inc with the lite version aptly named “Microwind“. Once the user form is filled out with minimal information, unhealthy various tools can be downloaded with an assortment of papers including a 4-bit microprocessor example. The lite version of the tool is somewhat limited, but there are some simple layout examples. Furthermore, this is the tool used to demonstrate all of the examples in Basic CMOS Cell Design (Amazon) and Advanced CMOS Cell Design (Amazon) by Sicard (author of the software) and Bendhia. I have read most of the first book and am working on the second one and will write a short review when both are completed. So far, the first (Basic) one is all-right for a reference but requires some thinking to understand a few of the layouts. The image above is a example layout for a 3-bit DAC.
For me, site speed of construction is the ultimate goal for prototyping circuits. This often involves perforated prototyping boards with components and wires flowing everywhere giving an impression of a clump of hair. It got the job done, however, it was increasingly difficult to troubleshoot with each additional kludge and even harder to have somebody else understand the board. Even if they had the schematics. Some time ago I was pointed to an excellent article by K7Q0 describing Manhattan Building Techniques. The style involves taking a copper clad board and gluing smaller pieces of copper clad board to it to mount components on. Techniques are discussed to make this mounts for single point connectors to more complicated dual in-line connectors. The overall result is that the circuit looks much cleaner and is easier to diagnose. A secondary benefit is that the circuit typically includes a ground plane and the possibility of power planes for reduced noise. The chief downside is that the prototype board takes longer to produce, however, this may well be justified.
( manart.pdf )