μblog: engineering from the trenches

I am coming to the realization that the PLL is one of the most under-appreciated components used in almost all aspects of electrical engineering. In many PLL applications, such as clock generation, the ratio of the output frequency to driving frequency is below ten, but a well designed PLL can push this ratio to several orders of magnitude. Finally, very special regard must be held for designers of very low frequency PLLs since keeping track of things for tens of milliseconds or more is very difficult in the analog domain. This is not to discredit designers of very fast (>500MHz) PLLs where the high frequencies tend to bring out non-ideal effects. First, here is a guide from Freescale Semi. that outlines the design of PLLs through a control theory approach based in the s-domain. Next, here is an application note written by Bob Pease in 1979 that describes some non-standard uses for PLLs as well as low (~1-10kHz) frequency design. Finally, here is report from MOSIS outlining a physical implementation of a given PLL design. (MOSIS tends to publish the projects that it funds internally for universities.)

( an535.pdf ) ( an-210.pdf ) ( digital_pll_report_1.pdf )

del.icio.us | digg