Tue 13 Mar 2007
Some time ago, I posted the schematics of Xilinx compatible parallel port to JTAG cables. Since then, I found more schematics that describe a complete Spartan-3 (or 3E) board including the same programming cable. These schematics include an FPGA (which can be as small as 100TQFP) and an SRAM chip with the intent of re-programming the setup at every powerup using JTAG. This can be extended by looking at page 67 of the V3.4 Spartan-3 datasheet. There are several methods of adding a configuration ROM to the device to ensure independent operation on power-up. Finally, the Xilinx ISE WebPACK can be downloaded to create basic bitmaps and actually send the code across providing a fairly limited, but free, development platform. Unfortunately, the Lattice Semi’s parallel port to JTAG cable is highly guarded proprietary information, so the same type of almost-free development solution is some ways off.
( livedesign_eb_schematics-xilinx_spartan.pdf )
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