μblog: engineering from the trenches

I spent some time on the phone with the dean of Engineering Science and Mechanics at PSU discussing my credit transfers and it turned out pretty well. All that I would have to get done is nine credits (three classes) of engineering science, two credits of seminars and twelve credits of thesis research. Pretty good deal! The downside is that I will move to State College, PA in July. Even though this is some time ahead, I have been pretty busy looking at living arrangements and so forth. It looks like I will try to focus more on research in the upcoming months to get as much done as possible before we move the lab.

On a side note, GMU is in the sweet sixteen, so wish us luck.

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So I found out yesterday that I am moving to Penn State University in July. Probably not going to get any hobby electronics done until I get my personal life sorted with this one.

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I finished soldering the prototype 8051 board and started working on getting the timing right to output a NTSC signal. As a reminder, each line has a ~5us blanking period, a ~5us front porch, and a ~52us active segment. It has been non-trivial to get the timing right using SDCC, so we will see what happens with this. Right now, I would be happy to generate an 8×8 checkered test patter on the screen, far short of implementing text-writing capability as I had originally hoped. That is to say, it is still possible, but I would have to do most of the coding in assembly to get the timing just right and the needed resolution, something I might not be willing to invest too much time into with parts for my msp430-ethernet project on the way. Hopefully I will have something to display on a TV tomorrow or day after.

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Finally got my 5V, PDIP 8051 development board designed and bread-boarded. I know I planned to go with the DS80C400, but it is more complicated and the Atmel works fine (for now). I ended up writing PAULMON2 very slowly onto on AT89S51 and using an 8KB NVRAM for program memory. The small trick is to wire the WR to WR and RD to PSEN, so the NVRAM is written like data memory and read like program memory. An OR gate between RD and PSEN outputs would effectively merge the separate program and data address space and make a very simple development target. As for development, I have been using sdcc (with –code-loc option) to generate code that starts at the start address of the NVRAM (0×8000). I will probably start working on the video code tomorrow try to solder the dev board together.

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I have been reading up on RFID design lately and came across some antenna design notes from TI. The two interesting concepts that they demonstrated are the ability to create a high performance, high-frequency (~13MHz) magnetic dipole antenna using copper tubing and the idea of using the coils from a tag in conjunction with a diode detector to measure transmission power. Why would this be interesting to anyone? The answer is two-fold: it is possible to create a simple detector for hidden RFID readers as well as detect some hidden tags. Current trend are such that tags are already incorporated in various security devices, however the security is either completely due to obscurity (see what happened to Kinkos recently) or is a very weak crypto-system (see TI troubles) so it is an interesting field for security research. There are also concerns that personal privacy might be invaded through tags, so detection of tags and readers can be useful.

( HFAntennaDesignNotes.pdf )

( HFAntennaCookbook.pdf )

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Another long day, here is a picture of my wafer, from MOS fabrication lab, in it’s current state. So far, we have grown a field oxide, opened source and drain windows, done diffusion for source and drain, and then etched the oxide separating them to grow a good gate oxide. It’s not quite pentium4 technology, but it’s still fun to make your own MOSFETS, only once.

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The in-circuit programmer that I was using for the 8051 (AT89S51) seems to have some problems with programming the chips correctly. The data is sent and verified, but then a memory map pulled from another method does not show the same results. To be more specific, I wrote a serial programmer in LabView that I used to verify the operation of the parallel-port ISP and found that the parallel-port ISP did not program all of the bytes correctly. Although the LabView programmer can program the whole chip without problems, it is very, very slow (doesn’t take advantage of page-write or DIO buffering.) I did manage to put PAULMON2 on one of the AT89S51 chips some time ago, so the current plan is to use that chip and external nv-ram to test code on or just move to a DS80C400, which has a built-in serial monitor. It seems that using a boot monitor is the easiest path to testing code on the 8051. For kicks, the poorly done LabView code is attached at the end.

( nchernyy-serial-programmer-slowio.zip )

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A few weeks ago, someone asked me about current-feedback op amps and I had the very basic answer that they had a low-impedance inverting input and relied on current, instead of voltage, to drive this input. This gave the op-amps higher slew rate (and bandwidth) at the expense of precision. A more thorough overview of these op amps can be found in chapter eight of Texas Instrument’s Op Amps for Everyone (linked below.) This is a four hundred page book and has some well written sections on various topics, including noise. An excellent read for those concerned with analog design.

( slod006b.pdf )

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My digikey order came in today, but some of the msp430-ethernet parts are on backorder until late March. I am not going to lay out the PCB and have it fabricated until I have these components, as the results can be devastating. To keep myself busy, I have been looking around at the Playstation3 specs released by Sony and have been thinking about designing a PS3 emulator based on a single 8051. I hope to have a playable Metal Gear Solid demo by the end of the month!

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