# How to pick decoupling capacitors and where to place them?

The standard response to this question has consistently been to “put a 0.1uF cap near the IC and then a larger cap in the vicinity of several ICs to charge the 0.1uF cap.” To extend this response, adiposity
some IC manufacturers have been including decoupling capacitors in their reference designs in the datasheets. Although this answers the how, it does not answer the why, so, I will try to give an overview of decoupling capacitor selection and placement for both digital and analog circuits.

First, lets assume a digital circuit that is running at a given clock frequency, f, whose ICs have a maximum switching frequency (bandwidth) b. If we look at the frequency spectrum of the transient current drawn from the power supply, the most obvious components are at the primary clock frequency f, as well as some harmonics of f. In addition, since most digital ICs have several gates that need to be sequentially driven to give an output, there are some frequency components at the bandwidth “frequency” as well as some harmonics. This second addition is very hard to estimate and is often left out of datasheets. Given sensitive equipment, it is sometimes possible to measure the transient supply current, it is also sometimes possible to get this information from the IC manufacturer. Now that we have a basic picture of the frequency distribution of the transient currents, we can briefly look at the amplitude. The best way to get these amplitudes is from the manufacturer, or if not there, experimentally. There are several methods for testing components for faults by looking at their transient supply current, so this information is both obtainable experimentally and is often available from the manufacturer. Given the transient currents, we can look at the effects of these currents on the supply voltage as a function of PCB layout. A standard number for trace inductance is 20nH for an inch of a 10mil trace. There are adjustments to this number due to trace geometry, vias, planes, so the number varies with different designs. At high enough frequencies, the transient currents generated can alter the supply voltage enough to cause improper switching within the IC and therefore corrupt the output. So the fundamental reason for the decoupling capacitor placement is to lower the effective inductance of the power traces and preserve normal operation. To do this well, the decoupling capacitor should be placed such that all current going to the IC from the power bus or planes passes the capacitor first. Sometimes, with planes, it is possible to use two capacitors to minimize capacitor to power pin spacing in high performance designs. Now there is the question of which capacitor to use. We first calculate how much transient voltage spikes our design can tolerate and see if we are within spec based on the inductance from the power pins to the capacitor. If the noise is within spec, then the capacitor type doesn’t really matter too much as long as it can source enough charge to cover the current transients. For fancier applications, we can tune the capacitors to specifically block noise on certain frequencies. From the previous treatment of capacitors, we know that non-ideal capacitors have both a capacitive and inductive component. We aim to see which frequencies most of the noise on the power lines is at and pick capacitors that have the lowest impedance at those frequencies, thereby giving the best AC performance. This is why some high-speed IC datasheets suggest several capacitors of different kinds to be put in parallel for decoupling purposes.

Analog IC decoupling is a slightly different beast. The spectral content of the transient currents is more stereotypical as the transients occur when the inputs and outputs switch, but not in between. With analog circuits, the power drawn is proportional to the power sourced to the load and fluctuations on the power supply lines are seen in the output. This clearly shows a feedback loop, which can add resonant noise to the output signal. Most analog ICs specify a power supply rejection ratio (PSRR) as a function of frequency, so it can be seen that there may be frequency ranges of interest where the PSRR is poor. That is to say, part of our signal could be in that frequency range or the power supply switching frequency could be there, both of which could potentially cause ringing. To get around this, we can apply the same capacitor tuning technique as described above when choosing the capacitor(s) for the job. Alternatively, we can figure out a voltage noise budget on our power supply lines, see if we are within spec by putting a capacitor close enough to the power pins, and if we are, simply put in a capacitor large enough to source the transient current.