Monthly Archives: February 2006

No free lunch

While Intel is moving to a 45nm feature (channel) size in 2007 and scientists are working on making devices even smaller, one may naively think that with shorter distances, we can have higher switching speeds and run the chips at 100GHz to meet the processing requirements for the “full” edition of Vista. The idea is constant field shrinking: we reduce critical device measurements in such a way as to maintain the same electric fields within the device. What this means, if half the channel length, width, and oxide thickness, we must also half the gate operating voltage and double the impurity doping concentration. We double the current density, but power density stays the same since we halved the operating gate voltage. This seems like a good deal: we reduce the device cross section area to 1/4th of the original size, increase switching speed (theoretically due to shorter path traveled by carriers) and maintain the same power density. So what’s the downside?

Unfortunately, nature really makes us work hard for the good things, so being able to use these smaller devices comes with a cost. First and foremost, you have leakage. There is the leakage component that comes from carrier tunneling through energy barriers and the component from the parasitic capacitances at higher frequencies. And we must keep in mind that there leakage from one device affects the neighboring devices, it doesn’t simply vanish. Furthermore, as the logic levels increase, we need some way to make them compatible with peripheral devices. We can either make all of our logic run at a lower level and incur the associated costs, or add extra level shifting logic, which might impede performance so that it is better to avoid the smaller devices in the first place. Don’t forget that as device size shrinks, their fabrication becomes more of a statistical process, the device to device parameters will have more fluctuation as compared with large devices. Furthermore, it is difficult to make doping profiles vary sharply enough to meet the constant field criteria since the dopants diffuse after injection. This is not to say that there is no hope, many of today’s semiconductor manufacturers are maintaining quasi-constant fields while shrinking their devices. That is to say that they shrink the device dimensions, but perhaps keep the logic levels the same at the expense of developing a gate oxide replacement with better permittivity and using silicon-on-insulator processes. So bottom line is that it is possible, but very difficult, so keep this in mind next time someone tells you about the shortly forthcoming 100GHz chips.

Pre-amplifier tomfoolery

Spent most of the day today playing with the pre-amplifier design. The design uses the same instrumentation amplifier chips (ina2332) for both large and small electrodes, however, this becomes problematic. The ina2332 is a dual amp chip, where each instrumentation amplifier is based on the two-op-amp design and is physically small, so there are worse parasitics when compared to larger three-op-amp designs. One of these parasitics is input bias current, which in this case is 1-10pA. Sourcing this kind of current is no problem for the larger electrodes, but has become problematic with the micro-meter sized electrodes. As a result, I designed a module to use two ina116 chips in place of one of the ina2332. These chips are single channels and are a few times larger than the ina2332s, but, they are less noisy and require only 10fA of input bias current. By making a few estimations and writing out the electrochemistry I-V relationships, one can attribute 100-400uV of voltage noise to the side-effects of a 10pA input bias current and how they are more manageable with a 10fA bias current. The lesson for today is that 10^-12 is small, but not insignificant.

On the transmission line effects of PCB traces

Here is an older application note from the former Motorola semiconductor division regarding transmission lines effects of PCB traces. A more thorough source of information is the MECL Design Handbook, but this is a good reference with both theory and examples. If the rise or fall times of your designs are approaching the round trip (source to farthest load back to source) with loading, then transmission line effects of PCB traces must be taken into account.

( AN1051.pdf )

Simple sound monitor

One of our experiment rooms, where some experiments are sensitive to sound, is shared with some other groups. To make matters worse, the room is periodically cleaned and maintained by lab technicians. As a result, sometimes it is hard to tell if recorded EEG signals are due to neural activity of the subject caused by some internal mechanisms or if it is due to external sound stimuli. To help alleviate this problem, I designed a simple narrow-band microphone amplifier to plug directly into our acquisition system. Continue reading

How to pick decoupling capacitors and where to place them?

The standard response to this question has consistently been to “put a 0.1uF cap near the IC and then a larger cap in the vicinity of several ICs to charge the 0.1uF cap.” To extend this response, some IC manufacturers have been including decoupling capacitors in their reference designs in the datasheets. Although this answers the how, it does not answer the why, so, I will try to give an overview of decoupling capacitor selection and placement for both digital and analog circuits. Continue reading